The increased operating speeds of electronic systems has made synchronous random access memories (RAMs) a preferred device for the storage of data that must be accessed rapidly. Synchronous RAMs operate in synchronism with a system clock. In a typical read operation, an address is latched on the rising edge of the system clock, and memory cells are selected according to the address. The selected memory cell data is then coupled to a data output path and finally driven on output pins for use by the system. Synchronous RAMs can be particularly effective in "burst" modes, in which the data of consecutive addresses is driven on output pins on consecutive clock cycles.
The minimum delay between the application of an address and the availability of output data will determine the maximum read operating speed of a synchronous RAM. Thus, reducing the delay required to provide output data allows for a faster, and hence a more desirable memory device. In addition, due to the data bandwidth advantages of burst mode, the ability to provide rapid bursts of data is also highly desirable.
The last portion of a data output path is usually the circuit that physically drives a data output pin. Such circuits are commonly referred to as output drivers or buffers. Referring now FIG. 1, a portion of a prior art output driver is set forth in a schematic diagram and designated by the general reference character 100. The output driver 100 drives an output node 102 between a first logic level and a second logic level by coupling the output node 102 to a high power supply voltage VDD or low power supply voltage VSS, respectively. The prior art output driver 100 is shown to include a p-channel metal-oxide-semiconductor (MOS) high drive transistor P100 having a source-drain path coupled between the output node 102 and the VDD voltage. In addition, an n-channel MOS low driver transistor N100 has a source-drain path coupled between the output node 102 and the VSS voltage. The high or low drive transistor (P100 or N100) is activated to couple the output node 102 to the VDD or VSS voltage, respectively.
The operation of transistor P100 is controlled by a high pre-drive circuit, shown in FIG. 1 as 104. The high pre-drive circuit 104 includes a p-channel MOS transistor P102 in series with an n-channel MOS transistor N102. The common drains of transistors P102 and N102 are coupled to the gate of high drive transistor P100. In a similar fashion, the operation of transistor N100 is controlled by a low pre-drive circuit 106, which includes series connected p-channel MOS transistor P104 and n-channel MOS transistor N104. The common drains of transistors P104 and N104 are coupled to the gate of low driver transistor N100. The gate connection of transistor P100 to its respective pre-drive circuit is shown as charge control node 108. The gate connection of transistor N100 to its respective pre-drive circuit is shown as discharge control node 110.
It is noted that in order to be able to rapidly drive the relatively high resistive and capacitive load presented by an output pin, the high drive transistor P100 and low drive transistor N100 are typically very large devices. As a result, the gates of transistors P100 and N100 present a relatively large capacitance to their respective pre-drive circuits (104 and 106). Thus, the speed with which the drive transistors (P100 and N100) can be turned on and off (and hence the speed at which data can be driven on the output node 102) depends upon the speed at which the high pre-drive circuit 104 and low pre-drive circuit 106 can change the voltage at the charge and discharge control nodes (108 and 110), respectively. Because of this, transistors P102, N102, P104 and N104, while not as big as the very large driver transistors P100 and N100, can be large devices relative to other transistors of the synchronous RAM.
The high drive control circuit 104 is shown to receive a hidrvoff.sub.-- signal, which is low when high drive device P100 is turned off, and hidrvon signal, which is high when the high drive device is to be turned on. The timing and generation of the hidrvoff.sub.-- and hidrvon signals can impact the speed of the output driver 100. In the same manner, the low drive control circuit 106 timing is controlled by a lodrivon.sub.-- signal and lodrvoff signal. The hidrvoff.sub.--, hidrvon, lodrivon.sub.--, and lodrvoff are generally synchronous with the system clock signal.
In addition to fast operating speeds, the power consumption of a synchronous RAM is an important feature. While high output buffer operating speeds can be achieved by using large transistors, the switching of such large devices, and those devices which generate control signals (such as the hidrvoff.sub.--, hidrvon, lodrivon.sub.--, and lodrvoff signals), can result in relatively high current consumption. Due to the multiple number of output buffers on a synchronous device, the resulting power consumption can be considerable.
Due to the considerable impact an output buffer can have on the operating speed of a synchronous device, there is always a need for fast synchronous output buffer circuits. At the same time, it is also desirable to include output buffer circuits that do not consume relatively large amounts of power.